Assume a CPU has a 4-stage pipeline

 Assume a CPU has a 4-stage pipeline (i.e. stages for Fetch, Decode, Execute, Store) and each stage takes 1 clock cycle. Assume instruction A is a WHILE LOOP test, and instructions B, C, D are inside the WHILE loop block and have been speculatively loaded into the pipeline. But on executing A, the processor discovers the loop will terminate so B, C, D should not be performed. Draw the pipeline for the next 6 clock cycles.